1. Technical Field
The subject matter described herein relates to the initialization and calibration of time-interleaved analog to digital converters (ADCs).
2. Description of Related Art
Time-interleaved ADCs (TI-ADCs) are used in very high speed communication systems, e.g., hundreds of Megasamples per second and beyond. A TI-ADC processes an input signal at a sampling rate Fs using N sub-ADCs, each operating on time-synchronized samples at a slower sampling rate of Fs/N. Outputs of the N sub-ADCs are interleaved to a cumulative output.
A significant problem with high speed TI-ADCs is mismatch among sample and hold (SH) circuits and sub-ADCs. Common causes of mismatches are component and trace length mismatches, which may result in resistive, capacitive, inductive and voltage mismatches. Mismatches are often quantified in terms of DC offset, gain offset and timing skew. Gain offset and timing skew may be quantified as bandwidth mismatch, where transfer function responses of SH circuits and ADCs are not the same across a frequency range.
Various techniques have been employed to mitigate timing skew, each of which has drawbacks. One technique requires a periodic or permanent training signal, which increases power requirements. Another technique requires foreground calibration, including a foreground calibration signal, extra hardware and a procedure that takes each SH circuit and ADC group offline for periodic calibration, resulting in link disruption, increased chip area, increased cost, increased power consumption and increased complexity. Another technique requires oversampling and an empty band in the sampled signal to estimate timing skew, which is incompatible with high speed transceivers without increased costs in terms of power and throughput. Another technique requires long finite impulse response (FIR) filters, which increases costs in terms of area and power consumption. Another technique requires parallel equalizers, which increases power consumption and requires knowledge of the received signal.